This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-78796, filed on Mar. 20, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile memory circuit comprising an automatic erase function, and more particularly to a nonvolatile memory circuit that has a memory capacity which is not an exponentiated number of two and that is capable of preventing hangup during an erase operation.
2. Description of the Related Art
In response to readout, programming and erase control commands which are supplied from the outside, flash memory, which is semiconductor nonvolatile memory, executes operations that correspond to such commands. More particularly, erase commands include chip erase commands, which erase all the sectors in the memory regions, and sector erase commands which erase designated sectors thereof. Memory regions comprise a plurality of sectors and a plurality of memory cells are provided in each sector.
On account of being nonvolatile memory, flash memory stores data contents which need to be kept for long periods such as system programs and control data, and the like. Flash memory therefore comprises a protect memory for storing protection information so that the data contents are not erased by mistake. The protect memory, which corresponds to each sector, stores protected states for prohibiting erasure of these sectors and unprotected states enabling erasure of these sectors. Further, before erasing given sectors in response to an erase command, the protection information in the protect memory which corresponds to these sectors is checked such that an erase operation is performed only to those sectors which are in an unprotected state.
FIG. 1 is a schematic constitutional view of a conventional flash memory. Memory arrays 14, which comprise a plurality of memory cells, comprise a plurality of sectors 0 to n, and the outputs of the sectors are supplied to a sense amp/verify circuit 18. A protect memory 16 for storing protection information P(0) to P(n) which corresponds to each of the sectors is also provided, and protect signals Pout, which represent the protection information read out from the protect memory 16, are supplied to a memory control circuit 20. The memory control circuit 20 is a type of processor known as a state machine which controls memory readout, programming and erasure in response to a given control command CMD.
A circuit which especially relates to erase operations is shown in FIG. 1. The memory control circuit 20 sets a sector address counter 10 to the maximum address in response to a chip-erase command. A sector address group SAdd, which is outputted by the sector address counter 10, is supplied to a decoder 12. The decoder 12 decodes the sector address group and then controls any one of sector select signals SEC0 to SECn to the activation level. Protection information in the protect memory 16 which corresponds to the sector select signal at the activation level is read out, whereupon a protect signal Pout is supplied to the memory control circuit 20.
Upon confirming that this protect signal Pout represents an unprotected state, the memory control circuit 20 supplies an erase signal S21 to the erase circuit 22 such that erase stress is applied to the selected sector. After the erase stress is applied, erase verification for the erasure of this sector is conducted by the verify circuit 18 and a verify result signal S18 is supplied to the memory control circuit 20. In the erase verification, if it cannot be verified that the erasure of all the memory cells in the sector is complete, the above-described erase stress application and erase verification are repeated. When the erase verification yields a pass, the memory control circuit 20 supplies a decrement signal S20 to thereby decrement the sector address counter 10.
On the other hand, upon detecting the fact that the protect signal Pout represents a protected state, the memory control circuit 20 does not erase this sector, but decrements the sector address counter 10 by means of the decrement signal S20 to thereby decrement the sector address group SAdd, and moves to an erase operation to the next sector. In the next sector also, the protection information is confirmed, and if this protection information represents an unprotected state, the memory control circuit 20 performs the erase operation, but in the case of a protected state, the memory control circuit 20 skips the erase operation.
The memory cells of the flash memory are, for example, constituted by MOS transistors that comprise a floating gate. A low threshold voltage state in which charge is not stored in this floating gate corresponds to an erased state (data xe2x80x9c1xe2x80x9d), and a high threshold voltage state in which charge is stored in this floating gate corresponds to a programmed state (data xe2x80x9c0xe2x80x9d).
Here, in an erase operation, erase stress is applied to a memory cell to thereby extract charge from the floating gate, such that the threshold voltage drops. Consequently, when the charge in the floating gate is adequately extracted, the threshold voltage drops sufficiently and a drain current flows in the cell transistor, which yields a pass in the erase verification. In cases where the charge extraction is not completed despite the erase stress being applied a predetermined number of times, subsequent erase stress application is not performed, and a hangup signal indicating this fact is generated internally. The fact that an erase error has occurred is communicated by outputting this hangup signal to the outside. Once a hangup signal is outputted, the memory chip is considered to be defective and can no longer be used.
Flash memory normally has a memory capacity that is an exponentiated number of two. For example, when the data bus width is 8 bits and an address is 24 bits, a flash memory has a 16 megabyte or 128 megabit capacity. That is, 128 megabits are equivalent to 227. Here, if the capacity of each sector is the same, the number of sectors is also an exponentiated number of two, such that for a chip erase operation, all the sectors are selected by sequentially decrementing the sector address from a maximum value to a minimum value.
FIG. 2 shows a flash memory that has a memory capacity that is not an exponentiated number of two. The flash memory shown in this figure is also constituted having a data bus width of 8 bits and addresses A0 to A23 of 24 bits, but the memory regions only total 96 megabits (12 megabytes), that is, 226 less than 96 megabits less than 227. In the figure, the memory A regions, which are indicated using solid lines, are 64 megabytes and 32 megabytes respectively, and are memory regions that actually exist. Further, the memory B region (32 megabytes), which is indicated using a dotted line, exists as an address space but does not actually exist. Such a memory is sometimes employed in cases where special restrictions exist in the system in which this memory is installed.
In a memory of this kind which has a memory capacity that is not an exponentiated number of two, the sector (n) and sector (nxe2x88x921) in FIG. 1 do not exist, for example. Consequently, in response to a chip-erase control command, and, the sector select signals SECn to SEC0 are scanned by sequentially decrement the sector address counter 10. When the sector select signals SECn and SECnxe2x88x921 are selected, because the sector (n) and sector (nxe2x88x921) which correspond to these sector select signals SECn and SECnxe2x88x921 do not actually exist, same cannot pass the erase verification. As a result, a hangup state (erase error) is assumed even though such chip is not defective.
Therefore, if the constitution is such that, at the time of a chip erase operation, a sector address is sequentially decremented (or incremented) such that sectors are selected in sequence, in a memory having a memory capacity that is not an exponentiated number of two, it is to be expected that, when nonexistent sectors are selected, the erase verification will not yield a pass and an erase error will occur.
Accordingly, an object of the present invention is to provide a nonvolatile memory circuit that is capable of preventing the above-described occurrence of an erase error.
In order to achieve the above object, one aspect of the present invention is a nonvolatile memory circuit, comprising: memory regions, which contain N (N is a plurality) of the sectors, N not being an exponentiated number of two and the sectors having the same capacity; a sector selection circuit for decoding a sector address and selecting the sector which corresponds to the sector address; and a memory control circuit which, in response to an erase command, executes an erase operation to the selected sector and, upon verifying that the erasure is complete, sequentially changes said sector address to select the next sector, wherein, when a sector that does not exist in the memory regions is selected, said memory control circuit selects the next sector without performing an erase operation to the nonexistent sector.
According to the above aspect of the invention, when a sector that does not exist in the memory regions is selected, because the memory control circuit selects the next sector without performing an erase operation to the nonexistent sector, the memory control circuit is capable of preventing the occurrence of an erase error due to a non-verification of the erasure completion, when this nonexistent sector is selected.